Hiespana - Hierarchical simulation of nanoelectronic systems for controlling process variations
Fraunhofer ITWM
Motivation
With the transfer from micro- to nanoelectronics the control of production deviations can not keep pace with the reduction of the absolute sizes of semiconductor devices.
This results in a drastic increase of relative parameter variation in the system and thus an increasing refuse of produced circuits due to system behaviors beyond the specifications. Since the systematic detection of effects of process variations via experiments is expensive and often restricted, it is possible to use simulations as comprehensive and cost-saving analysis of the problem:
The data of devices, which is produced in a given process sequence, can be pre-computed by process and device simulations. These data can be used for extraction of circuit parameters that determine the circuit behavior. If a process step is changed the effects on the device and the circuit can be calculated. Thus simulations enable designers to estimate and minimize effects of parameter variation, which allows decisive steps for the optimization of nanoelectronic devices and systems in advance.
Parameter tolerances on system level
In this Fraunhofer project the aim is to transfer extracted circuit parameters and their distributions to system level and to use them for model reduction as well as verification of the system.
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- Density function of two correlated parameters
Due to the extension of the interface between Cadence (commercial software tool for design of electronic circuits) and Analog Insydes (own software for symbolic analysis of electronic circuits) it is possible to transfer the information of a circuit, its parameters and corresponding distributions. The generated symbolic model equations can be used for a large signal, small signal or sensitivity analysis of the circuit. The latter one yields an approximation of the variation of the output behavior depending on the parameter distributions. Additionally the model equations can be reduced with respect to parameter distributions by a mixed numeric-symbolical algorithm. This is done using statistical error functions, to guarantee a good approximation of the original system. The symbolic form as well as the statistical behavior of the model are kept. The resulting behavioral model allows more efficient simulations and analyses of the system, due to its decreased complexity.
As an example of a system with parameter tolerances a voltage limiter circuit is considered, which limits the output voltage to 3.5 V. The dimensioning of the seven MOSFET transistors and the two resistors are afflicted with tolerances. After applying the numeric-symbolical reduction routine the simulation time is shortened by factor 12.
The diagram shows the result of a Monte Carlo simulation of the original and the reduced model. With increasing input voltage the circuit limits the output voltage to 3.5 V.
Further Information
- Type of Project: Fraunhofer Project
- Project Partners:
- Fraunhofer EAS/IIS
- Fraunhofer IISB
- Fraunhofer IMS
- Fraunhofer SCAI
- TU Wien
- Duration: Januar 2008 - Januar 2011
- Hiespana Homepage
- flyer (pdf) [ PDF 1.7 MB ]

