STX – Stencil- and Tensor Accelerator

Energy-Efficient Supercomputer Systems Made in Europe

The Stencil and Tensor Accelerator (STX) is a project, led by a team of Fraunhofer ITWM, in which we develop energy-efficient supercomputer systems based on European technology together with our partners. The focus is on a consistent hardware software co-design approach. Together with our SpinOff – UNEEC Systems GmbH – European supercomputer technology shall take a leading role worldwide.

In doing so, we make use of the latest RISC-VOpen Source hardware developments. Our holistic approach includes a proprietary System-on-Chip, PCIe card (Peripheral Component Interconnect Express) and HPC rack architecture. Through the co-design approach, the STX system concept combines an innovative architecture, highest energy efficiency and easy programmability for highly parallel simulation applications.

Energy Efficient Accelerator for Digital Twins

Simulations have become an important part of developing, monitoring and analyzing products and processes. They are used in both science and industry to calculate and predict complex relationships or interactions – whether in the field of engineering for the production of efficient wind turbines, vehicles optimized via simulations based on fluid dynamics, or in the area of climate or weather forecasting, as well as in the discovery of new materials or medicines.

These calculations digitally map reality as accurately as possible and require increasingly powerful supercomputers to do so. Despite the ever-shrinking technologies in chip development, the power consumption of the systems is increasing. The fastest supercomputers already exceed 20 megawatts.

In order to continue to provide more performance in the future, we rely on the usage of acceleration hardware to a large extent. These offer many performance and efficiency advantages for parallel applications. However, we are facing the following challenges:

  • The focus of technologies is shifting toward artificial intelligence.
  • Companies are accepting efficiency losses in order to continue offering high performance gains in new hardware generations.
  • The scaling of new chip manufacturing technologies offers significantly lower improvements in energy efficiency than on older technologies.
  • There are continuously increasing costs for design and manufacturing.

STX – Comprehensive System Concept

This is where the development of our STX system comes in. We use our many years of experience in the division »High Performance Computing« (HPC) at Fraunhofer ITWM to develop a complete system concept – starting with our own high-performance processor architecture up to the complete system. In doing so, we additionally benefit from the open source technologies in the field of hardware and software, which have gained significantly traction and maturity over the last ten years. Of particular note is the free RISC-V instruction set architecture (ISA) used by the ETHZ Pulp architecture. We are building on this work to develop a complete System-on-a-chip (SoC), design (GlobalFoundries 12LPP technology), PCIe Gen5 based plug-in card, rack insert, and overall system.

Our initiative is based on a »System-on-a-Chip« approach.
© Fraunhofer ITWM
EPAC1.5 testchip with STX IP on evaluation board

At the software level, we extend open source projects such as the LLVM compiler and the OpenMP runtime environment to allow the system to be programmed as easily as possible. Our simulation and emulation results show that we can achieve up to four times more efficient throughput per watt for industry-relevant applications by using a consistent hardware-software co-design approach compared to the current state-of-the-art.

In the medium term, the developments will also lead to an HPC system »Made in Germany«, so that parallel to our own developments, supply chains will be established in Germany and Europe. In this way, we are contributing to the establishment of a new industry in Europe and securing sovereignty in key technologies such as high-performance processors and system design.


Involved in the project are:

Other partners from industry and academia are also on board within the various projects.

Cooperation and Funding

These developments are made possible by:

  • public projects on European level (European Processor Initiative – EPI, funding number 101036168, duration: since 2018 until the end of 2025 and The European Pilot, funding number 101034126, duration: end of 2021 until early 2026)
  • national activities (STXDemo [only available in German], runtime: September 2022 to August 2025)
  • Fraunhofer internal support (STXMod runtime: since 2022 to mid 2024)