AI Model Determines Hardware Energy Consumption
But how exactly can the networks that meet the defined requirements and specifications be found? “There are different search strategies in this regard, and we use an evolutionary approach. We start with ten different randomly selected networks, train them and check how well they work. We then select the best networks and mutate them to create new network variants. We repeat this process until we have found the best network. This procedure is called automated machine learning,” explains Dr. Jens Krüger, who conducts research at the Competence Center — High Performance Computing at Fraunhofer ITWM and who led the project together with Prof. Dr.-Ing. Norbert Wehn from the TU Kaiserslautern. The researchers are extending this process, known as automated machine learning, to include a holistic approach that considers not only the neural network but also the hardware, since the AI model influences the energy consumption of the hardware.
Krüger and his team use programmable chips, FPGAs (Field Programmable Gate Arrays). These can map the neural networks, implement a variety of circuits and achieve the best possible execution of an optimal algorithm. The FPGA can be reprogrammed any number of times and is distinguished by various characteristics that are considered in the search for the optimal neural network. “In this respect, the project name HALF — Holistic AutoML for FPGAs — reflects the core aspect of our approach,” says the researcher. Using a software tool developed at TU Kaiserslautern, the neural network is transferred to the FPGA and is then able to automatically evaluate the ECG data. This approach has resulted in a new unifying methodology that is not only more energy-efficient than before, but also enables a reduction in development time for optimal neural network topologies and corresponding FPGA implementations. The software tools developed are suitable not only for FPGAs, but also for a wide variety of chips and environments.